The present invention relates, in general, to a clock monitor circuit and method. More particularly, the present invention relates to an integrated circuit and method for monitoring an input clock signal and providing an indication of the loss thereof to a microprocessor (MPU).
In an MPU controlled system, loss of an input clocking signal to the MPU may result in undesirable continued operation. This continued operation despite the loss of the clocking signal will, in turn, result in erroneous system operation which, in certain instances such as automotive or aircraft applications, could have potentially disastrous ramifications. Therefore, it is highly desirable to closely monitor the input clock signal to insure reliable system operation.
In this regard, there has been described a "Clock Failure Monitor Circuit Employing Counter Pair to Indicate Clock Failure Within Two Pulses", U.S. Pat. No. 4,374,361 issuing to Holden on Feb. 15, 1983. However, the system therein described is unduly complex, depending as it does on several different inputs and the use of six JK flip-flops. By the use of such circuitry, the device therein described is also not readily integratable with the microprocessing unit itself.